A semiconductor die (also called an "integrated circuit" chip or IC chip), with electrical circuitry formed therein can be mounted on a "ball grid array" (BGA) substrate using, for example, flip chip (also called "controlled collapse chip connection") structure 111 (FIG. 1A), wire bond structure 112 or tape automated bond (TAB) structure 113 described in "Ball Grid Array Technology", edited by John H. Lau, McGraw-Hill, 1995 that is incorporated by reference herein in its entirety. See also U.S. Pat. Nos. 5,420,460, 5,409,865, 5,397,921, 4,940,181 and 5,216,278.
FIG. 1B discloses a BGA package 120 with an IC chip 128 mounted on BGA substrate 125's first side 121 using wire bond structure 112 (FIG. 1A), and an array (also called "area array") of solder balls 122A-122J (where J is the number of balls) attached to BGA substrate 125's second side 123. BGA substrate 125 has a number of plated vias 125A-125K (where K is the number of vias) that electrically couple IC chip 128 to solder balls 122A-122J. BGA package 120 is typically assembled independent of, and then mounted on a structure, such as a printed circuit board 126.
Lau states at page 38 of his book referenced above "[a]s the PCB technologies push themselves to smaller plated vias, better tolerances, and finer lines and spaces, this next-generation BGA can result in carriers that can theoretically be the same size as the chip in the horizontal dimensions."
Although theoretically possible, many practical difficulties preclude manufacture of such chip sized carriers or packages. For example, the diameter of a plated via in an IC package limits the number of vias that can be formed in a given area, which in turn limits the smallest possible size of an IC package.
Moreover, the cost of fabricating the smallest possible IC package using conventional processes is very high, as compared to the cost of making a larger IC package. Such conventional processes include use of a glass-fiber embedded polymer (such as bismaleimide-triazine ("BT") from Mitsubishi Gas Chemical Corp. Japan) as a core layer. The core layer typically has a thickness of 2 milli-inches to 30 milli-inches. Such a core layer provides structural support to an IC package typically built around the core layer.
Use of such a core layer requires the associated steps of drilling via holes, and plating the drilled via holes. Such drilling and plating steps typically account for the majority of the cost of forming a BGA package or a printed circuit board using conventional processes and materials.